This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.